Cadence + Ixia: Solutions for Ethernet Network Processor Design VerificationNeeru BansalThu, 02/28/2019 - 13:16![IxVerify]()
Adequately testing Ethernet IP during design verification is an increasingly complex undertaking as network processor designs evolve to meet demanding requirements for faster IO, higher throughput, larger port counts and advanced features such as programmability and in-network telemetry.
Solution Briefs
Cadence + Ixia
Test – L2/3
